1. Field
Exemplary implementations of the present invention relate to semiconductor design technology, and more particularly, to a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a system including the non-volatile memory device.
2. Description of the Related Art
Recently, there is an increasing demand for non-volatile memory devices that can be electrically programmed and erased and that do not need a refresh function to rewrite data at specific intervals. Furthermore, in order to develop a large-capacity memory device capable of storing a large amount of data, active research is being carried out on technology for the high degree of integration of memory devices. Here, programming refers to an operation of writing data into a memory cell, and erasing refers to an operation of erasing data written into a memory cell.
In order to increase the degree of integration of memory devices, a NAND flash memory device, in which a plurality of memory cells are coupled in series (i.e., a structure in which a drain or a source is shared by adjacent cells), thus forming one string, has been developed. Unlike a NOR flash memory device, the NAND flash memory device sequentially may read data. The programming and erasing of the NAND flash memory device are performed by controlling the threshold voltage of a memory cell while electrons are injected into or discharged from the floating gate of the memory cell using an F-N tunneling method.
Meanwhile, write amplification (WA) refers to a difference between the amount of physical data transmitted from a host to a flash memory device to be written and the amount of logical data used within the flash memory device. The reason why there is a difference between the amount of physical data and the amount of logical data is due to the basic operation of the flash memory device, in which writing is performed by the page, whereas erasing is performed by the block. The difference may also be due to an operation, such as a wear-leveling operation or a garbage collection operation performed to improve performance within the flash memory device. This is because data needs to be moved or rewritten within the flash memory device irrespective of the amount of data supplied from the host. For example, referring to FIG. 1, assuming that the amount of physical data transmitted from a host to a flash memory device in order to be written is 4 Kb, the amount of logical data written within the flash memory device can be 16 Kb.
For these reasons, it is necessary to minimize an operation, such as the movement of data or rewriting that can become the cause of WA. However, the number of operations, such as the movement of data and rewriting that can become the cause of WA, is increased because the size of the page buffer of a recent flash memory device is increased.
From a graph (A) of FIG. 2, it can be seen that a relatively large amount of time is consumed if the read and output of data, the input of data, and a program are continuously performed within a flash memory device.
Accordingly, as shown in graph (B) of FIG. 2, a scheme of performing a parallel input of data in an operation section, in which data is programmed, can be suggested to reducing the consumed time. Likewise, as shown in a graph (C) of FIG. 2, a scheme for outputting and inputting of data in parallel, in an operation section in which data is programmed, is suggested.
In order to apply a scheme, such as that shown in the graph (B), to a flash memory device, however, a cache operation must be performed through an additional buffer, such as a cache buffer, while a program operation is performed. This scheme is problematic in that a large current consumption may be generated. That is, there may be a problem in that a large current may be generated because the two operations must be performed at the same time. This problem may become severe, as a flash memory device operates at higher speed.
Furthermore, if a scheme, such as that shown in the graph (C), is applied to a flash memory device, a large current consumption may be generated. Therefore, the scheme shown in graph (C) of FIG. 2 cannot be implemented in an existing flash memory device because a program operation and a data read operation cannot be performed at the same time. That is, since a program operation and a read operation are directly connected to memory cell arrays and performed in an existing flash memory device, the execution of the read operation during the program operation or the execution of the program operation during the read operation is physically impossible.